1. Field of the Invention
The invention relates generally to the integrated circuit power and ground routing and, more particularly, to a novel power and ground routing of integrated circuit (IC) chip devices that utilizes aluminum layer to form power or ground lines for distributing power across the IC from an off chip source to various blocks within the IC, thereby reducing the IR drop (or voltage drop) of the integrated circuit chip devices and improving the chip performance.
2. Description of the Prior Art
In the processes for designing a large-scale integrated semiconductor circuit device, respective blocks of the device are generally designed in parallel to complement device characteristics with one another. During the designing the large-scale device, the building-block type of method is utilized, in which the circuit of the device is divided into a plurality of circuit blocks and each of the circuit blocks is thus designed at the same time. The overall design of the device is then carried out by integrating these constituent blocks.
An integrated circuit (IC) usually has a larger number of circuit blocks and multiple levels of conductors are used to distribute power and signals from off the IC to the circuit blocks within the IC, between the circuit blocks, and between cells within each circuit block.
The conductors are formed by lithographically patterning a layer of conductive material to form conductive lines as viewed from above the IC substrate. The conductive layers with conductive lines formed therein are isolated by an insulating layer so that lines of one layer which cross another layer do not physically or electrically contact each other. When it is desired to electrically connect a conductive line formed in one layer to a conductive line formed in another layer, a conductive via is formed extending through the insulating layer between the two conductors.
The conductive layers typically have different sheet resistances, with the lowest level (layer 1 or M1) having the highest sheet resistance and the highest level having the lowest sheet resistance. This is due to technological processing constraints such as smaller thickness at the lower layers. The different sheet resistances have influenced routing, for example, with the higher sheet resistance, lower layers generally being used to make connections which are relatively close (e.g. within cells or blocks) while the higher level, lower sheet resistance layers are used to make longer connections, such as between points in different blocks.
FIG. 1 is an enlarged top view of a conventional IC chip device with six levels of copper metal layers, wherein merely a small part of a particular circuit block of the IC chip device is illustrated for the sake of simplicity. As shown in FIG. 1, a circuit block 10 has power (VDD) ring 12 and ground (VSS) ring 14 disposed along its perimeter. The power ring 12 and ground ring 14 are either formed in the sixth-level metal layer (hereinafter M6) or the copper metal layer that is one level lower than M6, i.e., M5. By way of example, the power ring 12 is formed in M6, while the ground ring 14 is formed in M5. In such case, some of the other lower levels of copper metal layers, for example, from the second-level copper metal layer, i.e., M2, to the fourth-level copper metal layer, i.e., M4, may be used for signal routing.
Within a center region of the circuit block 10 that is surrounded by the power ring and ground ring, a so-called “mesh” interconnection network 20 is provided. The mesh interconnection network 20 consists of a plurality of substantially orthogonal horizontal lines 22 and longitudinal lines 24. Through the mesh interconnection network 20 and respective via stacks 32 and 34, the power or ground signals are provided from respective power or ground rings to the cell level devices such as transistors or regions which are fabricated in or on the main surface of the semiconductor substrate (not shown) and are not equally spaced from the ring. The horizontal lines 22 and longitudinal lines 24 of the mesh interconnection network 20 are respectively formed in either M5 or M6 in this exemplary case.
In addition, in current copper processes, a layer of aluminum disposed under a passivation layer is mainly used to provide a bondable interface, an aluminum bond pad, atop a copper bond pad formed in the topmost copper metal layer of the integrated circuit chip in order to prevent oxidation of the underlying copper bond pad. In some cases, the layer of aluminum disposed under the passivation layer may be used to form so-called re-distributed layer (RDL) to re-distribute the aluminum bond pad to other location primarily for flip-chip applications.
The prior art approach of using the topmost two levels of the copper metal layers, i.e., M5 and M6, for power and ground routing induces that the voltage drop (or IR drop) is unavoidably high. This is partly due to that M5 and M6 have different thicknesses and different sheet resistances (Rs). Typically, M5 is much thinner than M6, and thus has a higher sheet resistance (roughly about two times of the sheet resistance of M6).
Therefore, there is a strong need in this industry to provide an improved power and ground routing for the integrated circuit chip devices that is capable of reducing the IR drop, thus improving the chip performance.